Numero dei candidati: 1

Criteri di valutazione titoli: Allegato 1

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Approvazione atti: Decreto del Direttore del Dipartimento Prot. n. 205500 Rep. n. 77/2021 del 19/11/2021

Graduatoria*:

1. Filippo SEMENZA Punti 48/100 - Vincitore - Inizio attività 01/12/2021

* Ai sensi delle Linee guida per il conferimento di borse per attività di ricerca e alta formazione post-laurea Rep. n. 128/2018 Prot. n. 20943 – 05/02/2018:

- qualora il vincitore rinunci espressamente alla borsa si procede allo scorrimento della graduatoria (Art. 14)

- in caso di rinuncia da parte del borsista sarà possibile conferire un’ulteriore borsa di ricerca al successivo idoneo in graduatoria per un periodo minimo di 3 mesi (Art. 17 c. d)

All you wanted to know about FPGAs as compute accelerators.

Abstract

Nowadays, the use of hardware accelerators to boost the performance of software applications is a consolidated practice, and among others, GPUs are by far the most widespread. Despite of this, also FPGAs have been successfully deployed to process front-end experimental data, or to boost machine learning inference algorithms, and their adoption could become more common also for other kind of workloads in the next future.
In this seminar the architecture of FPGAs will be initially presented, along with the available programming frameworks for such devices.
Then, after a brief discussion about the problem of theoretically estimating FPGAs performance, it will be introduced FER (FPGA Empirical Roofline), a benchmarking tool developed here in Ferrara, able to empirically measure the computing performance of FPGA based accelerators. Empirical results measured by FER on several AMD-Xilinx Alveo cards will be shown and compared with other processors.
Eventually, actual use cases will be discussed as well, showing some of the applications which could benefit from FPGA accelerators, spanning from Deep Learning inference to custom data processing.